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職務名稱
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-- Minimum Required: BS in EE or CS and 3+ years digital IC design related area or EDA/ technology field. Has the experience of using Timing sign-off, synthesis tools.
-- Preferred Required: MS in EE, CS and 5+ years digital IC design related area or EDA/technology field. Has the experience of using the following tools:
Cadence - RTL Compiler, Encounter timing system, NC-Verilog, Conformal, Spectre.
Or Synopsys - Design Compiler, PrimeTime, VCS, DFT, HSPICE |
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- MS/PhD in CS or EE, or equivalent experience
- Three to five years experience in developing large EDA software applications in C++, object oriented design, advanced data structures, optimization of algorithms, and interface designs. In depth knowledge of SystemC, Verilog and/or VHDL.
Preferred Experience:
- Experience in developing high level synthesis or sequential optimizations ia a plus. Must be highly motivated to initiate new ideas as well as to own and drive projects to completion. |
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- MS/PhD in CS or EE, or equivalent experience.
- Good knowledge in PhyVer, Cadence tools and Assura is obviously needed.
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- BS EE, CS or Industrial engineering related etc
- At lease 5 year direct sales experience
- Major account management experience
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- BS CS/EE +3 years required
- MS CS/EE +3 years preferred |
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- Solid knowledge in UNIX/Linux (application experience) and PC applications
- At least sufficient in oral and written English
- Good general communication skills, willing and interested in working in a multi-national/-cultural environment
- Proven experience in project management in multi person projects, project planning
- Ability to acquire thorough understanding of business environment of Cadence within six months
- Ability to execute autonomously a task on a remote customer site for extended periods of time, able to travel. |
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IDEAL PERSONAL PROFILE · Strong communication, interpersonal, facilitation, and presentation skills, with qualities in being strategic, analytical, hands-on and detailed, and able to act as a catalyst of change. · Assertive, positive, independent, self-inspired, and able to multi-task and learn effectively. · Proactive, flexible, and able to take initiative and work under pressure. · An influential leader who can motivate people and create a strong, energetic team spirit. · Having the presence, stature, maturity and credibility capable of commanding the respect and co-operation of subordinates, management team members, regional and corporate management, regulatory bodies, industry peers and associations, and the business community as a whole. · Above all, must have unquestioned personal and professional ethics. |
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- 6~8 Place & route experience with real project tapeout is a must. (SOCE or 3rd party APR tools)
- Pamiliar with STA, RC extraction, IR drop analysis is a plus.
- Familiar with low power, MCMM/MCMM-SI methodologies is a plus |
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Min education: MS/PHD in CS or EE, or equivalent experience.
Min experience:
1. Understand RTL (Verilog at least, VHDL is bonus)
2. Understand the digital implementation flow or concept
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- BS in Electronic or Computer Engineering
- 5+ years of experience in digital IC design and implementation
- STA (PrimeTime), hierarchical implementation flow, CPF MSV low power implemenation flow, floorplan / powerplan, physical synthesis, CTS, routing experience preferred. |
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-- Minimum Required: BS in EE or CS and 3+ years digital IC design related area or EDA/ technology field. Has the experience of using static/dynamic IR analysis, noise analysis tools and Sign-off Timing Verification .
-- Preferred Required: MS in EE, CS and 5+ years digital IC design related area or EDA/technology field. Has the experience of using the following tools:
Cadence - Voltage Storm, CeltIC-NDC noise analysis, ELC characterization (ECSM/S-ECSM).
Or Synopsys - PrimRail, PrimeTime SI,
Or Apache -Redawak
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Experience in developing synthesis, formal verification is a plus. Must be highly motivate to initiate new ideas as well as to own and drive projects to completion.
Three to five years experience in developing large EDA software application in C++, object oriented design, advanced data structures, optimization of algorithms. In depth knowledge of SystemC, Verilog and / or VHDL. |
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- MS/PhD in CS or EE
- Three to five years experience in developing large EDA software applications in C++, object oriented design, advanced data structures, optimization of algorithms, and interface designs.
- In depth knowledge of SystemC, Verilog and/or VHDL.
- In depth knowledge of Low Power Design Technology |
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