| Track |
Digital Implementation
/DFY/DFM |
Custom Design/DFM |
Track |
Logic Design and Advanced Verification |
PCB and Packaging |
| Ballroom A, 10F |
Ballroom B, 10F |
Ballroom C, 10F |
Ballroom D, 11F |
|
DESCRIPTION / PRESENTATION TITLE |
DESCRIPTION / PRESENTATION TITLE |
DESCRIPTION / PRESENTATION TITLE |
DESCRIPTION / PRESENTATION TITLE |
COMPANY |
SPEAKER |
COMPANY |
SPEAKER |
COMPANY |
SPEAKER |
COMPANY |
SPEAKER |
| 13:20 |
65nm Chip
Implementation
The Challenge to Meet Timing, Power, and DFM Closure |
From SpectreVerilog to AMS Designer/A Complete Design Flow for On-chip
Inductors using 3D Full-wave Technology |
13:20 |
Verification
Challenges for Multimedia SOC design - ¡§First Cut Work¡¨with Xtreme |
Adopt the
Lead-frame Based Package to SiP Software for Bonding Simulation |
GUC |
Peter Wei |
Cadence |
Ming-Te Yu/
Vincent Liu |
Avisionic
|
David Hsia |
Faraday |
WangJin Chen |
| 14:00 |
Spirits of DFY optimization
in APR platform tools |
Narrowing the Gap between Technology Development and Circuit Design |
14:00 |
Low Power Functional Verification and Closure of Power Intent |
Designing in DDR2
Memories |
TSMC |
Chung-min Fu |
Proplus
Solutions |
James Ma |
Cadence |
Neyaz Khan |
Foxconn |
T. Y. Ho |
| 14:40 |
Cadence
Encounter DFM/DFY solution |
Correlating and Simulating Substrate Parasitics in RFIC Circuit Design
|
14:40 |
HW-SW IP
Verification Flow Using ISX and Xtreme |
Advanced SiP/PoP
technology solution |
Cadence |
Frank Leu |
Cadence/TSMC |
Venkat Ramasubramanian |
ST Microelectronics |
Laurent Ducousso |
IBM |
Albert Chen |
| 15:20 |
Break (10 mins) |
| 15:30 |
Power Analysis on
Power Gating
Design using VoltageStorm |
Manufacturing Variability Analysis |
15:30 |
Verification
Planning and Management Techtorial |
Batchmode Timing Analysis |
Faraday |
James Su |
|
Nail Tang |
Cadence |
John
Nehls |
Foxconn |
H. C. Tu |
| 16:10 |
VCAD -
Services that increase Design System Productivity |
Next Generation Infrastructure
for
Schematic Back Annotation
in Virtuoso Analog Design
Environment |
16:10
|
Experiences with Developing a SystemVerilog Testbench for SoC Verification of Real Products |
EMC Rule Checker ¡V Shorten Cap Connection Length |
Cadence |
Olaf Zinke |
Cadence |
Madhur Sharma |
Freescale |
Frank Donner |
Foxconn |
Jason Hsiao |
| 16:50 |
People¡¦s Choice Presentation and Lucky Draw
Ending |
